In a pipelined network processor, data packets are processed in processing units, or processing elements, through which the data packets are transferred sequentially. In asynchronous pipelines, the admission to a processing element is given independently of admission to other processing elements. In known pipeline processors, incoming traffic is admitted to the sequence of processing elements so as to accomplish a constant bit rate, or admitted as quickly as possible without controlled admittance limitation, whereby limitations are given by processing capabilities. In cases where packets have different processing requirements, or are of different size, relatively large buffer capacities are required between the processing elements, since packets may be queued waiting for a time consuming process to be completed in the following processing element. In other words, since the maximum packet rate is given by the pipeline bandwidth (bits/s) and the minimum packet size, different packets may need to wait in different processing element FIFOs, making sum of PE FIFO sizes large.